1. Field of the Invention
This invention relates to the physical design process of designing hierarchical VLSI semiconductor chips. This invention is particularly directed at the placement of buffers with respect to localized placement and wiring contracts in order to enhance wiring track utilization.
2. Description of Background
A VLSI chip, which is a physical device, of course, may also be considered a logical entity in a hierarchical arrangement, particularly prior to actual manufacture of the chip. In one instance, for example, the chip may be defined as a logical parent entity having physical “unit” entities within its physical boundaries, where the units are logically defined as logical children entities of the parent chip. In turn, the units have macros within their physical boundaries, with the macros being defined as children of respective units.
From the foregoing, it should be appreciated these entities may be considered both entities in a logical sense and in a physical sense. That is, in a pre-fabrication stage, the entities have pre-defined, logical relationships among one another and are logical representations of what will become physical entities in a tangible IC chip. Even in the pre-fabrication stage, however, the representations are, themselves, physical in some respects, since they include data structures stored on a physical, computer-readable storage medium. So the entities discussed herein may be referred to as either physical or logical entities, although they are generally referred to herein as logical entities.
These logical entities have structural and functional properties that may be logically defined at a higher level of abstraction than mere physical circuitry, but that ultimately relate to circuitry, i.e., are decomposable into physical circuitry. For example, the logical entities may be defined in a very high level design language as Boolean logic blocks or equations. Nevertheless, ultimately they can be expressed in terms of very basic physical circuitry. These properties include data structures or instructions stored in a computer readable memory.
In this context, “wiring contracts” include rules governing the process of laying out wiring for VLSI chips, where chip space is “contracted” for wiring among a chip's hierarchically-related, logical entities. (Aspects of this process may also be referred to as “placing,” “routing,” and “allocating” wiring.) In other words, wiring contracts define certain wiring locations on the chip for interconnecting the distinct logical entities on the chip and define use of wiring tracks within those wiring locations, including allocation of the wiring tracks to the logical entities on a hierarchical level by level basis.
The term “wiring contracting,” as used herein, refers to a process or processes of allocating silicon space of the VLSI chip in the context of the chip design process or processes, particularly with respect to allocating wiring tracks of the chip.
As dimensions in semiconductor technologies shrink and frequency of operation increases, it becomes increasingly necessary to buffer parent nets in VLSI hierarchical designs, particularly in semiconductor chips. Whereas in older technologies it may have been possible to completely route wiring over a child entity without requiring a buffer, hi current technologies buffers are more often required. Consequently, silicon area must now be even more closely negotiated between parent entity and child entity. Additionally, lower levels of metal wiring must be more closely negotiated, so that the parent can access buffers.
Methods such as those described in U.S. Pat. No. 6,341,365, “Method for automating die placement of a repeater device in an optimal location, considering pre-defined blockage, in a high frequency very large scale integration/ultra large scale integration (VLSI/ULSI) electronic designs,” are aimed at finding optimal placement locations in unoccupied silicon area, but don't consider detailed aspects of wiring contracts that are advantageously taken into account in the present invention, data flow Methods such as US20020184607 A1, “Practical methodology for early buffer and wire resource allocation” and U.S. Pat. No. 6,826,740 B2, “Automated buffer insertion incorporating congestion relief for use in connection with physical design of integrated circuit” use congestion relief algorithms to re-route Sterner trees and more evenly disperse buffers. Although these concepts should help to generate more uniform buffer densities across a large region, they don't consider detailed aspects of wiring contracts that are advantageously taken into account in the present invention.
It should also be noted that choosing one Steiner tree over another does not necessarily guarantee that the congestion problem will improve as there are an extremely large number of possible Steiner trees for any given net.